NOISE, DISTORTION AND CROSSTALK
-156 dBV/rt. Hz maximum at 10 kHz RTI at maximum gain
(16nV/rt. Hz)
-120 dBV/rt. Hz maximum at 10 kHz RTO at minimum gain
(1 V/rt. Hz)
0.01% maximum at gains < 256
0.1% maximum at all gains
-100 dB at 1 kHz
INPUT AMPLIFIER
Differential, AC coupled
1 Mohm per leg (2 Mohm differential)
+/- 5 Vpk
+/- 12.5 Vpk
70 dB minimum at 1 kHz
to 4096 in steps of 2
(-12.04 dB to 72.25 dB in 6.02 dB increments)
+-0.05 dB (0.6%)
20mV equivalent RTO
HIGH-PASS FILTERING
Single-pole at 1 Hz (always present)
Single-pole 50 Hz or 2 kHz high-pass that can be by passed
2%
LOW-PASS FILTERING
Programmable linear-phase low-pass
Corresponds to decimation rates of 1, 2, or 4
Passband is 45% of output sample rate with < 0.001dB ripple
Greater than 96dB stopband attenuation
3 pole anti-aliasing filter designed to minimize group delay and
amplitude variation in passband
DIGITIZATION
8 per board with simultaneous sampling
Programmable 128KHz, 64KHz, 32KHz
24bit 2s complement
64:1
-3dB at 49% of output sample rate
CLOCK
Internal or external, software selectable
33.5544 MHz.
Up to four cards can be linked for 32 simultaneous sampled channels
PCI
Full sized PCI (other formats available on request)
PCI 2.1 32-Bit, 33 MHz, 3.3/5V signaling
32-bit packed mode
Bus mastering DMA
Bridge core on Spartan 3E FPGA
20 W from +3.3V, +5V, and +/- 12V supplies
Software Provided
Microsoft Windows
Linux distributions using version 2.6
kernels
Others on request
Standard character
device driver with
IOCTLs for control
and configuration