Rugged solutions engineered for the world's harshest environments
FPGA Design
Developed For Portability & Code Reuse Using Very High Level Design Languages
Characteristics
- OFDM 1024, 2048, or 4096 QAM256 Channels
- Direct sample RF at 622 MHz
- Reed-Solomon FEC & Interleaving
- QPSK w/ continuous parameter tracking
- 42 Mbytes/sec final data rate
- FFT Window synchronization
- Interpolative FIR Filter
- Interpolating Cascaded Integrator Comb (CIC) Filter
- Decimating Cascaded Integrator Comb (CIC) Filter
- Decimating FIR Filter
- Aux channels used for frequency synchronization
- Aux uplink QPSK channels
- Low phase noise clocking System
- PCI-Express Hard Core
- DRAM Memory
SDR FPGA
The Xilinx Spartan-6 FPGA is programmed to perform the digital functions of the SDR modem. The complete RF waveform is realized, with the support of off chip ADC & DAC clocked at 622 MHz.
Simply by reprogramming the FPGA, the actual radio & modem characteristics can easily be optimized or tuned for the application.
Simply by reprogramming the FPGA, the actual radio & modem characteristics can easily be optimized or tuned for the application.
Characteristics
- Data pipe for TDMA Satellite MODEM
- 5x Interpolative FIR Filter
- 90x Interpolating Cascaded Integrator Comb (CIC) Filter
- 77.76 M samples/sec I & Q IF
- Numerically controlled oscillator for up & down converter mixers
- DAC Management for 622 MHz RF
- 77.76 M samples/sec Hilbert Transform
- 90x Decimating Cascaded Integrator Comb (CIC) Filter
- 5x Decimating FIR Filter
- Unbiased truncation following filter bit growth
- Extensive DSP functionality
- Clock management
- DAC Management
- ADC Management
- PLL Control
- GPS UART interface x2
- SRAM interface
- PCIe interface
- DMA
- Interrupt generation
- Data timing
- 3 digital loopback modes
ORBCOMM SDR FPGA
The ORBCOMM SDR FPGA uses a Xilinx Spartan 3A DSP series FPGA, with embedded DSP and PCI interface clock domains to implement the transmit and receive data paths for a software defined radio. It interfaces with PCI bus for easy microprocessor connection, and interfaces with off chip ADC, DAC, PLL, SRAM, GPS, and PCIe peripherals, as well as RF controls.
Complex functions were implemented using proven Xilinx IP to reduce schedule and insure implementation is error free.
Complex functions were implemented using proven Xilinx IP to reduce schedule and insure implementation is error free.
Characteristics
- Parallel to serial converter
- Produces custom serial output waveform based on GPS PPS input
- Clock frequency can vary from 80 MHz to 240 MHz
- CPLD part chosen after design, synthesis, and simulation with back annotated timing to guarantee fit & functionality across clock frequency
CPLD
Even though CPLD functions are usually simple in nature, Colmek utilized the same tools and design methodology as FPGA designs, ensuring consistent and proven results.
FPGA Development Tools
Verilog is the preferred language for developing portable FPGA code that can be migrated to different Xilinx families, migrated to other suppliers such as Altera, and also migrated to CPLDs.
Additionally, it provides the migration vehicle for a prototype implementation to an ASIC, and also ensures easy migration from an obsolete component as the need arises.
Additionally, it provides the migration vehicle for a prototype implementation to an ASIC, and also ensures easy migration from an obsolete component as the need arises.
For FPGA simulation and synthesis into the target component Colmek uses Xilinx ISIM simulator.
ISIM provides the capability to simulate behavioral HDL as well as modeling with back annotated timing after design flow completion.
Furthermore, Colmek uses it as a core component of its design flow, as each implementation is thoroughly simulated using a test bench before it is actually verified on hardware.
ISIM provides the capability to simulate behavioral HDL as well as modeling with back annotated timing after design flow completion.
Furthermore, Colmek uses it as a core component of its design flow, as each implementation is thoroughly simulated using a test bench before it is actually verified on hardware.
On occasion, Colmek utilizes purchased FPGA development platforms, such as this one for the Spartan 6 Series Xilinx, to quickly jump to FPGA integration in advance of availability of the target platform.